The present invention relates generally to measurement techniques that are used in semiconductor manufacturing processes. More specifically, the present invention relates to techniques for measuring overlay error between different layers or different patterns on the same layer of a semiconductor wafer stack, as well as measuring other characteristics such as critical dimension (CD).
An overlay measurement generally specifies how accurately a first patterned layer aligns with respect to a second patterned layer disposed above or below it or how accurately a first pattern aligns with respect to a second pattern disposed on the same layer. The overlay error is typically determined with an overlay target having structures formed on one or more layers of a work piece (e.g., semiconductor wafer). The structures may take the form of gratings, and these gratings may be periodic. If the two layers or patterns are properly formed, then the structure on one layer or pattern tends to be aligned in a specific measurable orientation relative to the structure on the other layer or pattern. If the two layers or patterns are not properly formed, then the structure on one layer or pattern tends to be offset or misaligned with respect to this specific orientation.
There continues to be a need for improved techniques and apparatus for measuring and determining overlay.